High-speed 16-to-1 multiplexer implementation serializes data as fast as 50 gigabits per second
By Robert Schwanke
With today’s high-capacity systems, the need to reduce wide parallel buses to serial signals has become a vital necessity, particularly in test and measurement, telecommunications, data communications, satellite, and military and aerospace applications.
A parallel-to-serial (P/S) converter, often referred to as a multiplexer (mux) or serializer, can be used to convert an 8 or 16-bit wide parallel data bus, usually from an ASIC or FPGA, into a single, serial-bit signal. The serialized signal can then be transmitted across a densely packed PCB, over a chassis back plane, through a fiber-optic cable or through free space via a satellite, microwave, or free-space optics link.
Existing P/S converters made in traditional Gallium Arsenide (GaAs) and Silicon Germanium (SiGe) technologies typically have a data rate of only 1 to 10 gigabits per second and often include narrowband clock multiplier circuits. Most of the 10-gigabit-per-second devices are restricted to 10-gigabit Ethernet or OC-192 rates due to narrow band PLLs or DLLs.
Today however, 4:1 multiplexers made from commercially available Indium Phosphide (InP) technology that has been qualified for use in military applications and tested to be radiation tolerant, meet the exacting needs of designers working on test and measurement (ATE), high-performance communications like the new 100-gigabit Ethernet standard, computation, military, and research and development systems. The high performance and unique characteristics found in InP technology translates into devices that are well suited for use in any industry.
P/S converters are often used in the high-speed interface for broadband test instrumentation and communications. The P/S converter’s ability to convert low-speed, parallel data to a high-speed, serial data stream is used in broadband pattern generators and serial communications links. By using a high-performance P/S converter, system designers can extend the high-speed serial data rate from a few gigabits per second to 20 gigabits per second, or even 50 gigabits per second. The resulting system offers a significant increase in serial link capacity.
Four useful circuit implementations for multigigabit serializers are a 16:1 P/S for 10- to 50-gigabit-per-second operation; a 16:1 P/S for 100-megabit-per-second to 20-gigabit-per-second operation; an 8:1 P/S for 10 to 50-gigabit-per-second operation; and an 8:1 P/S for 100-megabit-per-second to 20-gigabit-per-second operation.
These circuits are widely used in 20-gigabit-per-second 16:1 broadband pulse pattern generators for test instrumentation; 50-gigabit-per-second 16:1 serializers for fiber-optic or free-space serial communications links; and 20-gigabit-per-second 8:1 or 16:1 broadband, backplane, or intra-system serial data links.
The first circuit, a 50-gigabit-per-second 16:1 P/S can be implemented using four 20-gigabit-per-second 4:1 serializers and one 50-gigabit-per-second 4:1 serializer. The 16 inputs of the four 20-gigabit-per-second serializers are the low-speed data inputs.
The four high-speed data outputs from the four 20-gigabit-per-second serializers feed into the four low-speed data inputs of the 50-gigabit-per-second 4:1 serializer. In this way, the high-speed data output will be the 50-gigabit-per-second serialized channel. The clocks are implemented by connecting the divide-by-four low-speed clock output of the 50-gigabit-per-second 4:1 serializer to the high-speed clock inputs of the 4:1 serializers, and the low-speed divide-by-four clock outputs of the 4:1 serializer can be used for synchronization and to clock the upstream device (ASIC or FPGA) driving the 16 parallel low-speed data lines.
The second circuit, a 20-gigabit-per-second 16:1 P/S, can be implemented much like the first circuit. The high-speed outputs from four 20-gigabit-per-second 4:1 serializers are fed into the low-speed data inputs on a fifth 20-gigabit-per-second 4:1 serializer that replaces a 50-gigabit-per-second serializer. The clocks can be used as defined in the first circuit.
The third circuit, a 20-gigabit-per-second 8:1 P/S, can be implemented in one of two ways. The high-speed outputs from two 20-gigabit-per-second 4:1 serializers can be fed into one 20-gigabit-per-second 2:1 selector/mux. The same high-speed clock used on the 4:1 serializers can be used to drive the 2:1 selector/mux with an appropriate phase delay.
In this implementation, additional timing margin can be acquired by offsetting the phase of the 4:1 serializer clock inputs by 180 degrees. Alternatively, the high-speed data outputs from four 20-gigabit-per-second 2:1 selector/muxes can be fed into the four low-speed data inputs of one 20-gigabit-per-second 4:1 serializer. While the first implementation requires fewer parts, the second implementation can be easier to implement because a synchronization circuit is not required.
The fourth circuit, a 50-gigabit-per-second 8:1 P/S, can be implemented like the second implementation for the 20-gigabit-per-second 8:1 P/S. The high-speed outputs from four 20-gigabit-per-second 2:1 selector/muxes are fed into the four low-speed data inputs of a 20-gigabit-per-second 4:1 serializer.
High clock and data rates, robust high-bandwidth differential CML I/O buffers, and a simple, straightforward architecture are key characteristics when using P/S converters as building blocks in broadband applications that require high-speed operation beyond a few gigahertz.
Robert Schwanke is a senior applications engineer at Inphi Corp. in Westlake Village, Calif. He has worked at Conexant/MindSpeed and Vitesse.
The difference between a digital mux and a serializer
Any discussion of novel circuit designs that can be created using P/S converters, must include a discussion of the difference between a digital multiplexer (mux) and a serializer.
A digital multiplexer is a circuit that has N “Select” inputs, 2N data inputs and one data output. Any one of the 2N data inputs can be selected to connect to the data output. The data on the selected input passes through the digital mux to the data output, retaining the same output data rate as the individual selected data input rate. Any data input can be selected, and although inputs are generally not selected sequentially, they can be. Input data is not latched within the mux and must be maintained throughout the desired bit time. Select lines are individually controlled and require an external control circuit.
In contrast, a serializer is a circuit with N low-speed data inputs, one high-speed data output, one low-speed clock output, and one high-speed clock input. This circuit is sequentially designed to select each of the N low-speed data inputs and connect to the high-speed output. The data from each of the low-speed data inputs is transmitted from the high-speed data output over a time span equal to that of a single low-speed data input bit time. Thus, the high-speed data output is transmitting data at N times the data rate of the N low-speed data inputs.
The high-speed clock input is used to generate the internal select lines, which are used to sequentially connect each of the N low-speed data inputs to the high-speed data outputs. The low-speed data inputs are typically latched on the chip to help alleviate timing constraints. A divide-by-N, low-speed clock output is generated from the high-speed clock input for use by upstream logic, usually an ASIC or FPGA, to generate the low-speed, parallel data fed into the serializer.
