Boeing eyes next-gen radiation-hardened space processor based on the ARM architecture
GREENBELT, Md. – U.S. government space researchers are asking the Boeing Co. to develop a next-generation radiation-hardened, general-purpose, multi-core space processor to meet on-board computing needs of future manned spacecraft and space robots.
Officials of the NASA Goddard Space Flight Center in Greenbelt, Md., have announced a $22.6 million contract to the Boeing Defense, Space & Security segment in St. Louis for the High Performance Spaceflight Computing (HPSC) Processor Chiplet program for NASA and U.S. Air Force manned and unmanned spacecraft.
This four-year project is expected to deliver a next-generation rad-hard space processor based on the ARM processor architecture to provide optimal power-to-performance for upgradeability, software availability, ease of use, and cost.
The HPSC project also will use Radiation Hard By Design (RHBD) standard cell libraries, as well as the ARM A53 processor with its internal NEON single instruction, multiple data (SIMD) design. Experts say a heterogeneous multi-core architectures using many different processor core types will not provide the best possible return on investment.
Applications for the HPSC processor will include military surveillance and weapons systems, human-rated spacecraft, habitats and vehicles, and robotic science and exploration platforms. System applications range from small satellites to large flagship-class missions.
Related: Air Force, NASA to develop rad-hard ARM processor for next-generation space computing
Space computing tasks of the HPSC processor will include command and data handling, guidance navigation and control, and communications like software-defined radio; human assist, data representation, and cloud computing; high-rate real-time sensor data processing; and autonomy and science processing.
Boeing will provide prototype radiation-hardened multi-core computing processor Chiplets, system software, and evaluation boards for Chiplet test and characterization. The Chiplets each contain eight general-purpose processing cores in a dual quad-core configuration, and interfaces to memory and peripheral devices.
System software infrastructure will support real-time operating systems and Unix/Linux parallel processing to support hierarchical fault tolerance ranging from single Chiplet deep-space robotic missions to multi-Chiplet -redundant human spaceflight missions.
The HPSC processor will include Serial RapidIO (SRIO) for high-bandwidth communications, and several interfaces to high-speed off-chip memory. The SRIO interfaces also can function as advanced microcontroller bus architecture (AMBA)-bus bridges to tile or cascade several processors to increase bandwidth or improve fault tolerance.
The SRIO interface also can extend the HPSC processor to other SRIO-enabled processing devices such as field-programmable gate arrays (FPGAs), graphics processing units (GPUs), and in the future to other application-specific integrated circuit (ASIC)-based coprocessors.
Related: Taking radiation-hardened electronics to new heights
Air Force and NASA experts have defined the ARM-based hardware and companion Linaro system software as the HPSC processor baseline architecture.
Today's radiation-hardened space processors typically are single-processor systems based on existing commercial or military computers. They operate at maximum required throughput, fault tolerance, and power levels. Air Force and NASA space experts, however, say they anticipate future missions that will require an increase in throughput and wider variations in throughput, fault tolerance, and power levels.
To do this Boeing embedded computing experts will develop a new space processor design that will provide orders of magnitude improvement in performance and performance-to-power ratio as well as the ability dynamically to set the power-throughput-fault tolerance operating point.
Future onboard space computers for manned and unmanned missions will require big improvements in vision-based algorithms with real-time requirements; model-based reasoning techniques for autonomy; and high rate instrument data processing.
Boeing will carry out a preliminary design phase, a detailed design phase, a fabrication phase, and a test and characterization phase. The project should lead to a processor behavioral model, prototype processors, processor evaluation boards, and system software.
A key goal for the HPSC project is the ability to trade dynamically between processing throughput, power consumption, and fault tolerance. The HPSC processor architecture sometimes will be inside a dedicated space-flight computer, and sometimes may be embedded in a science instrument or spaceflight subsystem.
The range of these applications can be from robotic science data processing to human rated applications employing ARINC-653 time space partitioning.
Fault tolerance management middleware will enable the processor to detect and log errors; remove services likely to experience hard failures; respond to uncorrectable errors; and implement n-modular redundancy, checkpoint/rollback, or other high-level fault tolerance.
For more information contact Boeing Defense, Space & Security online at www.boeing.com/defense, or NASA Goddard Space Flight Center at www.nasa.gov/goddard.
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John Keller | Editor-in-Chief
John Keller is the Editor-in-Chief, Military & Aerospace Electronics Magazine--provides extensive coverage and analysis of enabling electronics and optoelectronic technologies in military, space and commercial aviation applications. John has been a member of the Military & Aerospace Electronics staff since 1989 and chief editor since 1995.
