The ever-shrinking world of small-form-factor embedded computing

thermal management,” Straznicky says. “All of the standardization work that’s been done on 3U VPX ports offer to the Short VPX form factor.”

There also are industry discussions about increasing the pitch of the form factor so there isn’t a loss of usable real estate on printed circuit boards (PCBs).

“Part of the effort is creating a form factor that can go into smaller spaces than 3U VPX can, like round enclosures,” Straznicky says. “That’s emerged as a big requirement within SOSA. We’re currently talking about standardizing on a 1.2-inch pitch instead of the 0.8-inch or 1.0-inch pitch typical of VPX today.”

A smaller computer board has several advantages, Straznicky says. “With a 1.2-inch pitch, you can put mezzanine cards on the board and provide roughly the same amount of PCB space as you do with 3U VPX. To do that, you go taller in the Z dimension, while reducing depth. That makes it possible, for example, to fit the board into something like a 6-inch diameter tube.

Short VPX

This relatively small form factor also has its downside, Straznicky points out. “It won’t support XMC or PMC cards, since they are too long, but it will support FMC or FMC+ mezzanine modules. Another benefit of Short VPX is that it would be as rugged, if not more rugged, than 3U or 6U VPX, because of its small size. I would imagine that two-level maintenance would turn out to be an option for Short VPX, but it likely won’t be as attractive as 3U/6U VPX for two-level maintenance, but it’s hard to say at this point.”

Justin Moll, vice president of sales and marketing at embedded computing specialist Pixus Technologies in Waterloo, Ontario, says he agrees that open standards are driving development of SFF systems.

“The military/aerospace sector is pushing for significant performance upgrades in modular open standard architectures that provide more interoperability, efficient and quicker acquisition, and sustainment through increased commonality,” Moll says. “The SOSA effort is the primary driver in our industry to achieve these goals. From a backplane/chassis perspective, this means that the faster and hotter boards require more heat dissipation. Also, the backplanes are increasing in speeds to 40 Gigabit Ethernet, PCIe Gen4/5, and 100 Gigabit Ethernet levels. Especially with optical (VITA 66) and RF (VITA 67) interfaces on the backplane, there is less space for routing these high-speed signals. The SOSA requirements also allot for clocking, timing modules, and chassis managers.”

In 2019, the then-secretaries of the U.S. Army, Navy, and Air Force signed the Modular Open Systems Approach (MOSA) tri-service memo which states common standards enables information’s sharing between machines in different branches of the military is the natural continuation of SOSA’s efforts.

Mike Southworth, a senior product manager at Curtiss-Wright, says the tri-service memo has a rippling effect in U.S. Department of Defense (DOD) requests for quotation (RFQ) and requests for proposals for new platforms.

“The Government’s mandate and continued push for open architectures is now becoming explicit in RFQs,” Southworth says.

AI and small form factor

Artificial intelligence (AI) and robotics in the aerospace and military market will help drive the growth of small-form-factor embedded computing between 2021 and 2025, says Dan Mor, director of video and GPGPU product line for Aitech Defense Systems Inc. in Chatsworth, Calif.

“Real-time response applications, as often found in military and defense environments, are requiring systems that can perform AI processing at the sensors for AI at the edge and for autonomous operations — exponentially increasing computing requirements. This means rugged, SFF systems with exceptionally high processing abilities,” Mor continues. “Common challenges when performing complex computations, from load balancing and CPU choking to upgrading and overclocking, hinder the higher processing requirements of today’s military systems, which keep increasing the number of data and video inputs that need to be managed. And the footprint keeps getting smaller.

Blending AI and GPGPU has provided tremendous advantages for aerospace and defense systems designers, Aitech’s Mor points out. “Systems powered by AI using GPGPU can quickly perform many tasks, such as object recognition, classification, making conclusions and predictions, that not long ago were assumed to require human cognition. The use of parallel processing enables exceptional computation, lower power consumption and ultra-compact, rugged systems that go almost anywhere. The implementation of AI and the changing of conventional weapons to ‘smart’ battlefields will enhance the performance of existing platforms of armed forces around the world.”

Aneesh Kothari, vice president of marketing at Systel Inc. in Sugar Land, Texas, says AI and other technologies are driving performance demands even from SFF systems.

“With the proliferation in platform sensor integration, data collection, and immediate-future technologies involving AI and autonomy, customers require data center performance at the edge,” Kothari says. “Additionally, there is a significant need for reduced size, weight, and power (SWaP). Systel is meeting these demands by providing high-performance, fully rugged embedded edge computers, purpose-built for deployment in austere environments.”

In addition, Paul Quintana, associate director of global aerospace and defense business unit at Microchip Technology in Chandler, Ariz., says that 5G technology is helping to leverage AI and machine learning capabilities in SFF systems.

“For example, edge compute leveraging artificial intelligence and machine learning (ML) drives the trend to highly integrated and compute dense, secure, and low power microelectronics enabled by SOC and SOM [system-on-module] technologies. Second tier edge aggregation embedded compute needs will process increasing amounts of data within the same thermal envelop making use of the flexibility and power efficiency of SoC FPGA’s to meet the needs of near-term system needs, as well as future needs as requirements change.”

Mix and match

Pixus’s Moll says industry is able to combine 3U and 6U OpenVPX boards in the same chassis. This is done by leveraging a horizontal-mount chassis configuration 3U segment so that it can sit side-by-side with a 6U segment.

“For example, a 3U tall OpenVPX horizontal-mount chassis can support five sets of 3U OpenVPX boards and five sets of 6U OpenVPX boards, all at 1-inch pitch,” Moll says. These boards can be plugged into one monolithic backplane with options for VITA 66 and/or VITA 67 interfaces. Alternatively, the same enclosure can just be loaded in 3U OpenVPX boards.”

Placing more SFF computing power can be put into rugged chassis results in the need for greater cooling capabilities, points out Ram Rajan, the senior vice president of engineering at Elma Electronic in Fremont Calif.

“The most significant trends Elma is seeing in SFF is increasing the I/O options out of the box, of course, as we, as an industry, move more towards interoperability as well as continuing to deal with the challenges of heat dissipation,” Rajan remarks. “Thanks to ever-shrinking electronics, systems can be used in more compact environments, but this poses two major design hurdles:

Components are being consolidated into multi-purpose units, so that more components, aka capabilities, can then be added. But as more components are added, the result is more heat and less places for it to flow out of the system.

SFF platforms seek to house the most functionality in the smallest footprint. By design, as overall real estate condenses, the designer is left with less space for heat to be dissipated.

Rajan continues, “Enclosures are generally cooled through air cooling or conduction cooling, but recently the concepts of liquid and vapor cooling have come about, allowing for effective thermal management that can be tailored to specific applications.”

Lee Brown, senior director of C4S at Curtiss-Wright Defense Solutions concurred with Elma’s Rajan on the need to keep things cool in SFF systems like system-on-chip (SOC) and system-in-package (SIP) technologies.

“As things continue to miniaturize and power becomes more condensed thermal management expertise becomes all the more important. We have addressed and developed mitigating approaches for these challenges, so that boards using SOC and SIP devices can optimally perform and survive in military environments, as they ramp from cold to hot.”

Thermal management

Systel’s Kothari agrees that thermal management can be a challenge when it comes to embedded computers.

speeds to 40 Gigabit Ethernet, PCIe Gen4/5, and 100 Gigabit Ethernet levels. Systel utilizes proven thermal design board and chassis-level cooling methods to effectively and efficiently manage heat dissipation,” Kothari says. “Systel’s small form factor embedded computers can easily approach 200 Watts, all in a super dense, fully sealed system. Thermal management is of paramount importance, especially with system operating temperature ratings of up to +71 C.”

Moll from Pixus agrees with the need for heat management. “From a backplane/chassis perspective, this means that the faster and hotter boards require more heat dissipation,” Moll says. “Also, the backplanes are increasing in speeds to 40 Gigabit Ethernet, PCIe Gen4/5, and 100 Gigabit Ethernet levels. Especially with optical (VITA 66) and RF (VITA 67) interfaces on the backplane, there is less space for routing these high-speed signals. The SOSA requirements also allot for clocking, timing modules, and chassis managers.”

In addition to thermal management in SFF systems, Curtiss-Wright’s Marc Couture, who is the company’s director of its ISR business segment, says that signal integrity is also very important in an industry that is embracing a “commercial off-the-shelf” (COTS) mindset.

“Today, we have to use very expensive tools from a variety of vendors in order to solve cutting edge signal integrity problems,” says Couture. “It’s not just about routing power. There are other signaling issues, such as those involving memory lanes. Going from PCIe Gen 3 to Gen 4, and dealing with the associated higher data rates, will become increasingly difficult for smaller board vendors unless they can invest in these costly tools and they have the engineering staff with the requisite expertise. Leading COTS suppliers will continue to move forward, but smaller board houses will likely have a tough time keeping up with anything more than simpler, less challenging designs.”

Processing power

Luis Esparza, product manager for Abaco Systems Inc. in Huntsville, Ala., rugged systems segment, says that customers are asking for an increase in processing density while combining application specific processing with general purpose processing.

“Supporting advanced and sometimes very specific signal processing requirements on top of traditional compute routines. Enabling a diverse set of customer missions and tasks on a relatively common set of hardware,” says Esparza. “Customers from various markets are looking to Abaco to provide these sophisticated solutions that can survive the environments in an efficient high performing card or system product. We are seeing more combinations on-die of CPUs, GPUs, FPGAs, Analog, AI cores, etc. The close proximity of these functional blocks brings benefits in higher interconnect speeds, lower latency and lower power than equivalent discrete devices. SOSA is increasingly a driving force in the standardization of I/O and pinout.

“The trends are driven by customers and underlying technological advances. At Abaco we are rising to meet the challenge,” Esparza continues. “The budgets are quite constrained given the expanse of performance and pressure from near pears requires novel efforts to ensure a lower overall cost of ownership to advance the technology in the Military and Aerospace sector. Abaco is in a unique position to transform the commercial technologies into products that can enable our Military and Aerospace customers to develop, advance and Deploy in a timely and cost-effective manner. Many of our customers have decades invested in Intellectual Property and cannot afford to start new software development efforts every time a technology or sensor advances. We need to re-use IP where it makes sense and re-fresh or Invent what is needed to truly outpace competitors and adversaries. The need to do the same function at lower power or more work at the same power, combined with diminishing returns from Moore’s Law-type advances drives the need to go parallel, and to tailor the architecture to the task at hand.”