HRL Laboratories joins electronics cooling project for of 3D heterogeneous integration (3DHI) chip stacks
ARLINGTON, Va. – HRL Laboratories LLC in Malibu, Calif., is joining Teledyne Scientific & Imaging LLC and Northrop Grumman Corp. in a project to develop scalable thermal management technologies to help with electronics cooling architectures in the future that involve 3D heterogeneous integration (3DHI) chip stacks.
Officials of the U.S. Defense Advanced Research Projects Agency (DARPA) announced a $14.5 million contract to HRL Laboratories earlier this month for the Miniature Integrated Thermal Management Systems for 3D Heterogeneous Integration (Minitherms3D) project.
The Northrop Grumman Mission Systems segment in Linthicum Heights, Md., and Teledyne Scientific & Imaging LLC in Thousand Oaks, Calif., also won Minitherms3D contracts this month. The program seeks to revolutionize electronics cooling for 3DHI packages and significantly reduce thermal resistances within the 3D stack and external to the stack of 3DHI systems, while increasing volumetric heat removal.
Minitherms3D, sponsored by the DARPA Microsystems Technology Office, seeks electronics cooling technology scalable to an arbitrarily large number of high-power tiers in 3DHI chip stacks. HRL Laboratories, Teledyne Scientific & Imaging, and Northrop Grumman will handle the program's 18-month first phase.
Program goals include 3D stacking of five tiers with total heat dissipation more than 6.8 kilowatts with the heat rejection system limited to less than 0.006 cubic meters.
Continued rapid growth of compact high-performance microsystems is limited by inadequate integrated thermal management, including acquisition of heat from 3D integrated circuits, to the heat's transport and ultimate rejection to the ambient environment.
For example, the state of the art in 3DHI in high-performance computing typically uses one tier of logic and several tiers of high-bandwidth memory. Stacking of logic is currently limited to low-power tiers.
Three-dimensional (3D) stacking of several tiers of high-power logic and other functional blocks, including radio frequency devices, offers significant advancement in future microsystems, but today is infeasible because of insufficient in-plane and out-of-plane heat acquisition from each tier, and poor thermal isolation between functional blocks.
Unoptimized heat transmission and rejection also result in large overall size of electronics cooling hardware, which limits growth in system capabilities, particularly in radio frequency systems, image analysis, and high-performance computing applications such as artificial intelligence (AI) and machine learning.
The Minitherms3D project has two technical challenges: reducing thermal resistances within the 3D stack; and reducing thermal resistance external to the 3D stack.
Reducing thermal resistances within the 3D stack involves increasing in-tier heat transfer without increasing tier thickness. Regions of average heat flux more than 150 Watts per square centimeter along with localized hot spots more than 1 kilowatt per square centimeter in 3DHI tiers simultaneously must be managed thermally to maintain acceptable chip temperatures.
In a 3D stack, hot spot electronics cooling must rely on in-tier heat spreading, since interior tiers do not have direct access to top or bottom cooling. In a Si tier of 100-micron thickness, thermal conduction limits heat spreading to hot spot of 1-by-1 millimeter to 200 Watts per square centimeter with a temperature rise below 10 degrees Celsius over the rest of the tier.
Handling more intense hot spots requires increasing tier thickness or increasing thermal conductivity of tiers with processing compatible with very large scale integration (VLSI).
Reducing thermal resistances within the 3D stack also involves increasing thermal isolation between adjacent in-plane and out-of-plane functional blocks, as well as increasing heat removal from each tier while maintaining low thermal resistance.
Reducing thermal resistance external to the 3D stack, meanwhile, involves reducing link thermal resistance. Current approaches using thermal interface materials and cold plates have demonstrated 30 degrees Celsius per kilowatt of thermal resistance from the stack surface to the heat rejection component, posing a bottleneck in heat removal, and negating thermal resistance reduction inside the stack.
This approach also involves increasing volumetric heat rejection capability while reducing heat rejection resistance to air. For given convection conditions and ambient temperatures, the volume of heat rejection to the ambient air -- or a heat sink -- increases linearly with heat rejection.
Minitherms3D will be a four-year, three-phase program with 18-month phase 1, 18-month phase 2 option, and 12-month phase 3 option. Phase 1 will focus on hot spot mitigation for a stack of three equally powered tiers with total heat dissipation of four kilowatts. Phase 2 will demonstrate electronics cooling of a stack of five equally powered tiers, with total dissipation of 6.8 kilowatts. Phase 3 will demonstrate system level thermal resistance and volumetric heat rejection targets in a simulated application.
For more information contact HRL Laboratories online at www.hrl.com; Teledyne Scientific & Imaging online at www.teledyne-si.com/en-us; Northrop Grumman Mission Systems online at www.northropgrumman.com/who-we-are/business-sectors/mission-systems; or DARPA at www.darpa.mil.
John Keller | Editor
John Keller is editor-in-chief of Military & Aerospace Electronics magazine, which provides extensive coverage and analysis of enabling electronic and optoelectronic technologies in military, space, and commercial aviation applications. A member of the Military & Aerospace Electronics staff since the magazine's founding in 1989, Mr. Keller took over as chief editor in 1995.
