The pace of embedded computing technology development is placing pressure on satellite and spacecraft designers, who must deliver reliable systems at low costs.
Space is a dangerous place, especially when it comes to sensitive electronic components like microprocessors, solid-state memory, and network interfaces. The problem is radiation; space has a lot of it, and most modern electronic components were not designed to operate in a radiation environment.
Levels of radiation that occur in space can cause a variety of problems for electronic components, ranging from complete burnout to the occasional bit flip that can corrupt some data and render the reliability of even untouched data open to question.
There are ways to specially design radiation-hardened electronic parts to resist the effects of radiation, but it's expensive to do this. Moreover, overall demand for rad-hard electronic parts is relatively low, which can drive up their costs even more.
Then there's specially shielded packaging of electronic parts to keep radiation at bay. Not only is this approach expensive, but it also can be heavy enough to adversely influence launch costs. There are other ways of dealing with space radiation, ranging from redundant subsystems, selective shielding, and upscreening commercial off-the-shelf (COTS) electronics for enhanced reliability.
Among the challenges of space operations today are balancing electronics costs, capabilities, and reliability such that systems are good enough to operate in specific radiation environments for expected durations to meet mission requirements.
Space radiation effects
There are several ways that electronic parts designers can radiation-harden their devices. One of the most common is to harden for total-ionizing-dose radiation - or the amount of radiation the device is expected to withstand for its entire life before problems occur. A typical requirement is for 100 kilorads of total-dose radiation hardness.
The evolution of today's advanced electronic components, however, also is changing the total-dose picture. Specifically, the shrinking size of circuits on today's most modern chips is lessening their vulnerability to total-dose radiation.
"As technology nodes decrease in size - from 90 nanometers to 14 nanometers - total ionizing dose performance naturally improves," says Michelle Mundie, business area director of standard products at rad-hard specialist Cobham Semiconductor Solutions in Colorado Springs, Colo.
This phenomenon is a double-edge sword, however, because the steady shrinking of chip geometries also makes these devices even more vulnerable to other kinds of radiation effects, namely single-event upset (SEU) and single-event latchup (SEL). "Single-vent effects like latchup are becoming more of a problem, so we have to design for those effects," Mundie says. "Devices today are more sensitive to radiation at the gate and transistor level."
Single-event upset can corrupt data when a radiation-charged particle flips a data bit from a one to a zero, or vice versa, which corrupts data. SEU typically does not physically damage an electronic device, only the data it contains or that flows through it. Single-event latchup, however, can be damaging if it causes a short circuit that triggers thermal runaway. Device designers must consider these potential threats.
There are several design approaches to mitigating radiation effects, which include radiation hardening by design, selective shielding, redundancy, and error-checking. One of today's most notable rad-hard by design projects is the High Performance Spaceflight Computing (HPSC) Processor Chiplet program.
Rad-hard by design
Rad-hard by design involves designing an electronic component from the ground up to resist radiation effects. It can be one of the most expensive and time-consuming approaches, but sometimes it's the only solution for electronic components that are crucial for protecting human lives or safeguarding important orbital and deep-space missions.
U.S. government space experts are working with the Boeing Co. to create a new generation of radiation-hardened microprocessors for a wide variety of space applications to provide some of the most advanced processor technologies with broad industry and software support for future space missions.
Sponsors of the HPSC project are the U.S. National Aeronautics and Space Administration (NASA) and the U.S. Air Force Research Laboratory at Kirtland Air Force Base, N.M. Industry experts from the Boeing Solid-State Electronics Development segment in Seattle are carrying out the program, based on a $25.9 million contract awarded last March by the NASA Goddard Space Flight Center in Greenbelt, Md.
The HPSC program is intended to develop rad-hard microprocessor technology that will replace or augment previous generations of rad-hard microprocessors, such as the RAD750 from the BAE Systems Electronic Systems segment in Manassas, Va., and the RH-1750A, RH-32, and Advanced Spaceborne Computer Module (ASCM) from the Honeywell Aerospace segment in Clearwater, Fla.
Managing the HPSC project are experts at the NASA Jet Propulsion Laboratory (JPL) in Pasadena, Calif., led by Richard Doyle and Raphael Some. The NASA Goddard Space Flight Center is managing the HPSC contract.
The program is developing technologies for a next-generation, general-purpose, multi-core space processor to meet on-board computing needs of future manned spacecraft and space robots. The four-year project is expected to deliver a next-generation, rad-hard space processor based on the ARM processor architecture to provide optimal power-to-performance for upgradeability, software availability, ease of use, and relatively low costs.
Although previous generations of rad-hard space processors like the RAD750 have performed well for years, "there are needs now that are well in excess of what that processor can do," explains Wesley Powell, assistant chief for technology in the NASA Goddard electrical engineering division.
Today's radiation-hardened space processors typically are single-processor systems based on existing commercial or military computers. They operate at maximum required throughput, fault tolerance, and power levels. Air Force and NASA space experts, however, say they anticipate future missions that will require an increase in throughput and wider variations in throughput, fault tolerance, and power levels.
Commercially developed technology
"We're basing this device on commercially developed, well-supported IP, and making sure there is a wide user base and software support - something that is well-supported by industry," Powell says. Air Force and NASA experts have defined the ARM-based hardware and companion Linaro system software as the HPSC processor baseline architecture.
Boeing embedded computing experts will develop a new space processor design that will provide orders of magnitude improvement in performance and performance-to-power ratio as well as the ability dynamically to set the power-throughput-fault tolerance operating point.
The HPSC project also will use Radiation Hard by Design (RHBD) standard cell libraries, as well as the ARM A53 processor with its internal NEON single instruction, multiple data (SIMD) design. "You really need the ability to do radiation hardening by design, applied to standard cells, etc., that allow you to use a modern semiconductor process," Powell says.
NASA experts are looking at three broad application areas for the next-generation HPSC microprocessor: vision systems, model-based reasoning for on-board autonomy, and high-rate instrument processing, Powell says. Vision systems would involve space applications like obstacle avoidance. "We need to process imagery to determine where you should and should not land, and in real time," Powell says.
Model-based reasoning for on-board autonomy could enable spacecraft designers and space mission managers to migrate much of the mission-planning and resource-management tasking to the spacecraft, rather than rely on ground controllers for those jobs. NASA experts also are thinking ahead to future deep-space missions in which ground controllers may not always be in touch with the spacecraft, so must rely on the spacecraft to make some of its own decisions.
High-rate instrument processing involves demanding digital signal processing for sensors and instruments like synthetic aperture radar and hyperspectral electro-optical sensors. "We want to migrate some on-board data processing on-board the spacecraft so we can downlink data of interest, rather than just the raw data," Powell says.
In addition, NASA experts are looking to Boeing to develop enabling technologies for a space processor that not only is radiation hardened, but also can manage its own electricity demands to preserve power resources - especially on deep-space missions far from Earth.
Smart power usage
A key goal is the ability to trade dynamically between processing throughput, power consumption, and fault tolerance. "We want to be power-aware in our processor, and be able to ramp-down the processor for just what we need. That is kind of missing today," Powell says. "We are looking for the ability to tailor power, processing, and fault tolerance. Flexibility is one of the key objectives for HPSC."
Fault tolerance management middleware will enable the processor to detect and log errors; remove services likely to experience hard failures; respond to uncorrectable errors; and implement n-modular redundancy, checkpoint/rollback, or other high-level fault tolerance.
Additional applications for the HPSC processor will include military surveillance and weapons systems, human-rated spacecraft, habitats and vehicles, and robotic science and exploration platforms. System applications range from small satellites to large flagship-class missions.
Additional space computing tasks of the HPSC processor will include command and data handling, guidance navigation and control, and communications like software-defined radio; human assist, data representation, and cloud computing; high-rate real-time sensor data processing; and autonomy and science processing.
Boeing will provide prototype radiation-hardened, multi-core computing processor Chiplets, system software, and evaluation boards for Chiplet test and characterization. The Chiplets each contain eight general-purpose processing cores in a dual quad-core configuration, and interfaces to memory and peripheral devices.
"The period of performance is 45 months, so by late 2020 we're expecting Boeing to provide a processor chip or chiplets, packaged chiplets and bare die, and evaluations boards populated with chiplets to exercise the silicon," Powell says. "These chiplets will not be space-qualified; the focus of this project is on the silicon."
System software infrastructure will support real-time operating systems and Unix/Linux parallel processing to support hierarchical fault tolerance ranging from single Chiplet deep-space robotic missions to multi-Chiplet -redundant human spaceflight missions. "We also expect system software, including operating system, compilers, debuggers, a Linux operating system, and a real-time operating system," Powell says.
The HPSC processor will include Serial RapidIO (SRIO) for high-bandwidth communications, and several interfaces to high-speed, off-chip memory. The SRIO interfaces also can function as advanced microcontroller bus architecture (AMBA)-bus bridges to tile or cascade several processors to increase bandwidth or improve fault tolerance.
The SRIO interface also can extend the HPSC processor to other SRIO-enabled processing devices such as field-programmable gate arrays (FPGAs), graphics processing units (GPUs), and in the future to other application-specific integrated circuit (ASIC)-based coprocessors.
Powell says NASA and the Air Force will consider a flight-qualification program when the HPSC program concludes in late 2020 or early 2021. After that, it's reasonable to assume the technology will be ready for deployment. Powell speculates that HPSC technology could be deployed for at least 10 years before designers must look at a new generation of rad-hard microprocessors.
Looking beyond microprocessors
Outside the realm of the HPSC program, NASA experts are considering plans for additional radiation-hardened computer components, such as general-purpose graphics processing units (GPGPUs), field-programmable gate arrays (FPGAs), as well as volatile and non-volatile memory. The problem right now is funding.
For the HPSC program "we looked at a number of processing architectures, and the biggest bang for the buck was a general-purpose, multi-core processor," Powell says. For the future, nevertheless, "we have interest in some sort of paring of a general-purpose multicore processor with a rad-hard FPGA or GPGPU. There is interest, but we can't say that we have funding for that, but there's definitely interest.
"We're also interested in advancing volatile and non-volatile memory and networking rad-hard technologies," Powell continues. We have interest in developing a rad-hard ecosystem around that HPSC processor."
Looking to the future, companies with expertise in radiation-hardening GPGPUs, FPGAs, as well as volatile and non-volatile memory are urged to contact Wesley Powell, assistant chief for technology in the NASA Goddard electrical engineering division, at [email protected], or Richard Doyle, program manager of information and data science at the NASA Jet Propulsion Laboratory, at [email protected].
COTS electronics for space
While it's true that some space applications require the most expensive radiation-hardening solutions, the reality is that space systems designers must do the best they can to use commercially available electronic components for space applications.
Often this approach involves taking a hard look at whether the intended application is life- or mission-critical, the expected severity of the radiation environment in which the overall system will operate, and the duration of the planned mission, and then designing a radiation-tolerant system that's good enough.
Low-Earth orbit (LEO), for example, does not experience the same radiation levels that higher orbits or deep-space have. A growing number of LEO satellite applications today, moreover, have relatively limited life cycles. Some Earth-observation projects, in fact, are expected to last for less than five years.
"There's a push to put a lot more hardware on LEO orbits lasting from three to five years for space observation," says George Romaniuk, director of space product management at Aitech Defense Systems Inc. in Chatsworth, Calif. "The orbit is low, so the requirements are not that stringent. On the other hand, we see groups that will be for lunar or asteroid exploration beyond Earth orbit. They want to stay for a very, very long time (18 years, minimum) so the market is starting to segment."
Applications in lower-Earth orbits that may be of relatively short durations - and that could tolerate the occasional data upset - are a particularly promising market for COTS electronics suppliers, particularly for cost-sensitive applications like small satellites. "Our lives are basically lives of compromise," Romaniuk says. "We may not have $7 million to create something nice, but we have to piece together things that will provide performance and reliability."
Cobham has specialized for decades in selecting commercially developed electronic parts that are appropriate for some space applications. The company uses upscreening and a variety of other testing. The company started their rad-hard upscreening business about 20 years ago with a focus on solid-state memory, and now is expanding into microcontrollers and mixed-signal analog products.
"With changing market pressures from the small satellite industry, and the drive to smaller device sizes, a lot of the space market is looking at flying at COTS products," says Cobham's Mundie. "We knew the need was there, and our focus is changing to ensure we are offering our right products to the industry. It is a challenge for us to identify COTS products that will work in a variety of applications."
Multi-core redundancy
Some technological developments in the COTS computing industry are providing serendipitous advantages for space systems designers. Not only are deeply submicron geometries naturally resistant to total-ionizing-dose radiation, but modern multicore processor architectures also offer opportunities for system redundancy.
Embedded computing designers at the Curtiss-Wright Corp. Defense Solutions Division in Ashburn, Va., are using multi-core processors not to block radiation-induced single-event effects, but to recover gracefully without system disruption when upsets occur.
"Where we are now using multi- core processors to speed up com- puting, we also can use that to our advantage by running the same code in multiple cores," says Paul Hart, chief technology officer and technical fellow of avionics and electronics at the Curtiss-Wright office in Christchurch, England.
"We run main code in one core, and duplicate code in another core that run in lockstep," Hart explains. Running identical code in three separate processor cores enables the system to detect a malfunction in one core, shut down the offending core, and continue operating based on no detected malfunctions in the other two.
"If a single event does occur, it will cause one of the cores to lose lock," Hart says. "If that happens the higher-level supervisory system that operates above it will reset the device. It will take in the order of seconds to reboot a typical embedded application; while the upset core is rebooting, the other two carry on. You're fully recoverable after a bit flip."
Radiation creep
Hardening electronic systems to the effects of radiation isn't just a space problem any longer. Aircraft flying at altitude, at about 30,000 feet and above, also are starting to experience radiation-induced effects. "There are 500 times more neutrons at 30,000 feet than there are on the ground," points out Aitech's Romaniuk.
If commercial avionics systems designers aren't considering radiation hardening today, they soon will be. The shrinking of commercially developed microprocessor architectures and other electronic devices will continue making the problem worse.
