Varioscale to develop process verification of tiny integrated circuits
WRIGHT-PATTERSON AFB, Ohio - Microelectronics experts at Varioscale Inc. in San Marcos, Calif., are helping U.S. intelligence experts find ways of imaging tiny features on silicon integrated circuits for process verification and failure analysis.
Officials of the U.S. Air Force Research Laboratory at Wright-Patterson Air Force Base in Ohio announced a $23.8 million contract to Varioscale for the Rapid Analysis of Various Emerging Nanoelectronics (RAVEN) project. RAVEN focuses on developing an analysis tool capable of imaging minimum-size circuit features on a silicon integrated circuit chip for process verification and failure analysis.
The Air Force Research Lab awarded the contract on behalf of the U.S. Intelligence Advanced Research Projects Activity (IARPA), the research arm of the U.S. Office of the Director of National Intelligence, in Washington.
The RAVEN program encompasses four major areas for tool development: rapid acquisition of images from a bare die; real-time image analysis with in-situ feedback to minimize or eliminate rework due to image anomalies; innovative algorithms for reconstructing the images of individual device layers and the overall device; and computational resources for acquiring, moving, storing, and analyzing petabyte-size data files.
The project involves destructive and non-destructive image acquisition techniques.
Between 2011 and 2015, the semiconductor industry saw significant advances in the scaling of integrated circuits and 3D integration of several wafers, monolithically grown stacked circuits, and non-CMOS structures, officials say. Microprocessors of 14-nanometer size have been in production since July 2014 and 7-nanometer circuits were demonstrated at Albany Nanotech in early 2015.
Samsung, Taiwan Semiconductor Manufacturing Co. (TSMC), and GlobalFoundries have announced plans to ship production-quality 10-nanometer integrated circuits in late 2016. Intel plans to ship 10-nanometer integrated circuits in 2017, and TSMC plans to offer 7-nanometer chips in 2017.
Manufacturing at these technology nodes will require high-speed and high-resolution image acquisition for process verification and failure analysis.
The RAVEN program involves imaging metal, polysilicon, vias, contacts, shallow trench isolation (STI) regions, and dielectrics. The project may involve X-ray-based microscopes, high-brightness scanning electron systems, multi-beam scanning electron microscopes, non-scanned projected image electron systems, ion beam imaging systems, ultra-high-resolution interference optical microscopes, and several array AFM systems.
IARPA officials expect several companies to be involved in the RAVEN program.
The five-year RAVEN program has three phases. The two-year first phase will develop a laboratory benchtop or demonstration test tool. The two-year second phase will develop an alpha prototype tool and application demonstration. The one-year third phase will refine the initial prototype into a beta tool suitable for use in a research environment.
FOR MORE INFORMATION visit Varioscale online at www.varioscale.com, and IARPA at www.iarpa.gov.
John Keller | Editor
John Keller is editor-in-chief of Military & Aerospace Electronics magazine, which provides extensive coverage and analysis of enabling electronic and optoelectronic technologies in military, space, and commercial aviation applications. A member of the Military & Aerospace Electronics staff since the magazine's founding in 1989, Mr. Keller took over as chief editor in 1995.
