DARPA TRACE program using advanced algorithms, embedded computing for radar target recognition
WRIGHT-PATTERSON AFB, Ohio, Va., 24 July 2015. U.S. military researchers needed new ways of using computer algorithms and high-performance embedded computing (HPEC) for radar target recognition to identify military targets rapidly and accurately using radar sensors on manned and unmanned tactical aircraft. They found their solution from Deep Learning Analytics LLC in Arlington Va.
Officials of the U.S. Air Force Research Laboratory at Wright-Patterson Air Force Base, Ohio, announced a $6 million contract this week to Deep Learning Analytics for the Target Recognition and Adaption in Contested Environments (TRACE) program. The Air Force awarded the contract on behalf of the U.S. Defense Advanced Research Projects Agency (DARPA) in Arlington, Va.
The DARPA TRACE program has three goals: military target recognition on low-power aircraft; low false-alarm rates for targets deployed in complex environments; and rapid learning of new targets with sparse or limited measured training data.
In a target-dense environment, the adversary has the advantage of using sophisticated decoys and background traffic to degrade the effectiveness of existing automatic target recognition (ATR) solutions, DARPA researchers explain.
Aircraft attacks on relocatable targets require pilots to fly close enough to identify the targets visually before firing their weapons, which puts the aircraft at risk from ground-to-air missiles and other kinds of anti-aircraft weapons.
Although radar can take images of ground targets at safe standoff distances, the false-alarm rate of human and machine-based radar image recognition is unacceptably high. Existing target-recognition algorithms also require impractically large computing resources for use aboard manned and unmanned aircraft.
The result has been either to move the processing to remote ground stations or drastically reduce system performance to fit legacy aircraft computers.
To overcome these challenges, the TRACE program will develop an accurate, real-time, low-power target-recognition system that can be co-located with the radar to provide responsive long-range targeting for tactical airborne surveillance and strike applications.
The TRACE project lasts for 42 months and consists of two phases that will culminate in the flight demonstration of real-time radar target identification of stationary ground targets using one-foot resolution synthetic aperture radar imagery.
In the first phase, Deep Learning Analytics experts will develop advanced radar target recognition algorithms and design a low-power, real-time radar target recognition system. The program's second phase will enhance the algorithms and provide a real-time flight demonstration on low-power processor architectures.
Deep Learning Analytics experts have their work cut out for them, DARPA officials say. Despite significant military investments in radar target recognition over the past 30 years, few radar target-recognition systems have made it into widespread use in tactical applications.
Typically these systems have been too computationally complex for tactical aircraft. Algorithms have been too computationally complex or require too much run-time memory to fit onto legacy tactical aircraft computers.
Related: The future of high-performance embedded computing
Additionally, these kinds of systems have poor false-alarm performance such that they are inadequate for tactical surveillance applications. These systems also have not been adaptable. Learning to recognize new targets has taken too much time and computer power, and take a lot of operator and machine training with data and high fidelity models.
Deep Learning Analytics experts will try to overcome these limitations by exploiting recent advances in machine learning, low-power mobile computing architectures, and radar signature modeling. They will capitalize on the reduced runtime complexity of new recognition algorithms and increased computational efficiency of new mobile processors to reduce the run-time size, weight and power (SWAP) of radar target-recognition algorithms.
Company engineers will take advantage of emerging mobile computing architectures, including multi-core system-on-a-chip (SoC) systems combine general-purpose computing elements, such as multi-core ARM processors, with on-chip co-processors such as multi-core graphics processing units (GPUs) and field-programmable gate arrays (FPGAs), DARPA officials say.
For more information contact Deep Learning Analytics online at www.deeplearninganalytics.com, or DARPA at www.darpa.mil.
John Keller | Editor
John Keller is editor-in-chief of Military & Aerospace Electronics magazine, which provides extensive coverage and analysis of enabling electronic and optoelectronic technologies in military, space, and commercial aviation applications. A member of the Military & Aerospace Electronics staff since the magazine's founding in 1989, Mr. Keller took over as chief editor in 1995.
