DARPA aims at increasing embedded computing power efficiency from 1 to 75 GFLOPS per Watt
ARLINGTON, Va., 3 Oct. 2012. Scientists at the U.S. Defense Advanced Projects Agency (DARPA) in Arlington, Va., are looking to two technology companies to find ways to increase the power efficiency of high-performance embedded computing (HPEC) systems to from today's 1 billion floating point operations per second per Watt (GFLOPS/w), to 75 GFLOPS/w.
The DARPA Microsystems Technology Office (MTO) last week awarded a $6.3 million contract to SRI International in Princeton, N.J.; and an $8.7 million contract to Reservoir Labs Inc. in New York for the Power Efficiency Revolution For Embedded Computing Technologies (PERFECT) program, which seeks to overcome power efficiency barriers that limit the capabilities of military embedded systems.
Overall, the DARPA PERFECT program seeks to overcome limits on size, weight, and power (SWaP), and limited ability to dissipate waste heat, in embedded computing systems on military vehicles, ships, and aircraft. Additional PERFECT program contracts may be awarded.
Many intelligence, surveillance, and reconnaissance (ISR) systems today, for example, have sensors that collect far more information than can be processed onboard in real time, DARPA researchers say. This results in delayed processing of potentially valuable intelligence information, and sometimes discarding this kind of information altogether.
Current embedded processing systems have power efficiencies of around 1 GFLOPS/w, but experts say they believe at least 50 GFLOPS/w are necessary today, with requirements of 75 GFLOPS/w anticipated in the near future.
In the past, computing systems could rely on increasing computing performance with each processor generation, following Moore’s Law. This this free ride in processing performance increases, however, is over, DARPA scientists point out. Today, increasing clock speeds results in unacceptably large power increases.
The PERFECT program seeks to provide a power efficiency of 75 GFLOPS/w in embedded computing systems by taking a revolutionary approach to processing power efficiency, including near-threshold voltage operation and massive heterogeneous processing concurrency, while tolerating the resulting increased rate of soft errors.
The PERFECT program also will capitalize on anticipated industry fabrication geometry advances to 7 nanometers by developing a simulation capability to measure and demonstrate progress, since the program will not build operational hardware. While the PERFECT program addresses embedded systems processing power efficiencies, it will not focus on exascale processing issues, DARPA researchers say.
The current PERFECT program contracts concern seven elements: architecture, concurrency, resilience, locality, algorithms, simulation, and test and verification.
The architecture element focuses on improving embedded processing system power efficiency. Concurrency involves the hardware and software to support high levels of concurrency, or millions of concurrent execution streams. Resilience focuses on soft errors. Locality concerns keeping run-time data communication to a minimum by storing operands close to the referencing processors, in terms of energy. Algorithms concerns high-level software such as power kernels of embedded applications that minimize energy consumption.
Simulation will measure and demonstrate progress, since no operational hardware will be built in this program. Test and verification, meanwhile, is not part of these contracts.
The PERFECT program is in three phases. The first phase, which runs through 2013, focuses on proof of concepts to justify continuing development. The second phase, which runs from 2014 to mid-2015, will develop the technology and techniques to achieve 75 times greater processing power efficiency. The third phase, which runs from mid-2015 through 2017, will develop each technology or technique and provide the path to implementation.
For more information contact SRI International online at www.sri.com, Reservoir Labs at www.reservoir.com, or the DARPA Microsystems Technology Office at www.darpa.mil/Our_Work/MTO.
Follow Military & Aerospace Electronics and Avionics Intelligence news updates on Twitter
John Keller | Editor
John Keller is editor-in-chief of Military & Aerospace Electronics magazine, which provides extensive coverage and analysis of enabling electronic and optoelectronic technologies in military, space, and commercial aviation applications. A member of the Military & Aerospace Electronics staff since the magazine's founding in 1989, Mr. Keller took over as chief editor in 1995.
