Industry asked for efficient high-performance software compilers for heterogeneous computer architectures
ARLINGTON, Va. – U.S. military researchers are asking the computer industry to design software compilers able to handle the complexity of heterogeneous computer architectures to create high-performance efficient computer machine code.
Officials of the U.S. Defense Advanced Research Projects Agency (DARPA) in Washington, issued a broad agency announcement (HR001124S0035) for the Machine learning and Optimization-guided Compilers for Heterogeneous Architectures (MOCHA).
MOCHA seeks to build a new generation of software compiler technology that is optimized for heterogenous computational architectures with heterogenous central processing units (CPUs), graphics processing units (GPUs), and other accelerators.
Software compilers translate computer code written in programming languages into machine code that computer processors understand.
For more than three decades, hardware and software developers have relied on improving performance by increasing microprocessor clock speeds. Yet this scaling broke down in the mid-2000s and attention shifted to new approaches like multithreading.
Multithreading, however, also has its limits, and modern systems increasingly are using specialized co-processors and accelerators to improve performance. Worse, traditional compilers are not designed to generate efficient machine code for such heterogenous computer architectures.
To deal with this issue, software developers write unique code that takes advantage of specialized hardware, yet this approach reduces reducing productivity. Experts have found that extending compilers to handle heterogeneous computer designs is a manual task for compiler experts.
Adapting compilers is time consuming and error prone, does not address the challenge of taking advantage of hardware accelerators, and degrades attempts to upgrade mission-critical systems.
Related: Real-time software battle heats up in embedded systems design
For MOCHA, DARPA wants participants to use data-driven methods, machine learning, and advanced optimization to adapt compilers rapidly to new hardware with little human effort.
Participants also should develop new internal representations and programming languages that enable compilers to determine how to make optimal use of available hardware, rather than depending on humans to do so.
The MOCHA program envisions updating the three-tier architecture found in current compilers to include a front end, a middle end, and a back end.
A front-end that blends hardware-agnostic domain-specific languages, determines how to partition the computation into modules, and decides which modules should be directed to which CE.
Related: COTS board vendors make their DSP choices
A middle-end has intermediate forms, each likely associated with its own optimization suite, that is targeted to a specific type of CE. A back end generate code sequences that are subject to several performance figures like throughput, power consumption, and memory footprint).
End-to-end optimization techniques will manage search of possible implementations of a source program. The 36-month MOCHA program will begin in April 2025. Experts say technologies generated may require several years to mature.
The program's two key metrics are human effort reduction, and performance of the compiled code.
Companies interested should submit proposals no later than 26 Sept. 2024 to the DARPA Broad Agency Announcement Tool (BAAT) online at https://baa.darpa.mil. Email questions or concerns to DARPA at [email protected]. More information is online at https://sam.gov/opp/66cab3907c5b4cfcafbf102c5bb17eb6/view.
John Keller | Editor-in-Chief
John Keller is the Editor-in-Chief, Military & Aerospace Electronics Magazine--provides extensive coverage and analysis of enabling electronics and optoelectronic technologies in military, space and commercial aviation applications. John has been a member of the Military & Aerospace Electronics staff since 1989 and chief editor since 1995.
