The HI-6200 family provides a fully integrated and dual redundant MIL-STD-1553 BC/RT/MT interface solution which includes 1553 protocol, Error Correction and Detection (EDC) SRAM and dual transceivers in single 80-pin plastic 12mm x 12mm PQFP and QFN package configurations. The devices are register-level software compatible with legacy competitor devices, enabling re-utilization of existing software and resulting in minimal software development for new designs. The compact single-chip monolithic design offers a significant space and cost saving over the older traditional hybrid or multi-chip module approach, while offering additional feature enhancements and improved performance at an attractive price point. A cost effective RT-only version, HI-6202, is also available.
Features:
● Software compatible with legacy competitor architectures
● Improved high-performance host interface
● 64K Words SRAM w/ Error Detection and Correction (EDC)
● Operating Temperature -40°C to +85°C or -55°C to +125°C
● Single die for improved reliability
● Cost effective stable pricing
● Reduced lead times
A development kit demonstrating the key features of the device is available:
● ADK-62003: Evaluation Board for HI-62003.
