The digital receiver module has eight independent output channels of digital down-conversion (DDC) embedded in Xilinx Virtex-6 FPGA. As a flexible front-end receiver, this module implements the frequency translation and channelization for the IF band signal as the FPGA firmware.The firmware is implemented on the Xilinx Virtex-6 SX315T2 FPGA and consumes about 30% of the slice registers. The firmware is an optional item available for customizing the DDC project to include more features and processing capability after IP-DDC8i core.The optional firmware also includes the netlist version of IP-DDC8i core and Matlab/Simulink model for IP core simulation. The Modelsim model is provided for system simulation. Download Data Sheets & Pricing Now!
