80 PCIe Gen3 native links on backplane, it means 5 times more PCIe bandwith than what the Industrial PCs competitors may offer.ECRIN Systems has decided to support for its OPALE V2 range the new HDEC architecture introduced by TRENTON in 2016. At that time, this is the only technology able to manage 80 PCIe Gen 3 links of a PICMG 1.3 board equiped with two Xeon E5-2680 v4 !In addition to the standard features of OPALE V2 range, the new OPALE V2-HDEC version offers the following features:Dual Xeon E5-2680 v4 (28-Core/56-Thread)Up to 512Go DDR4 ECC Reg.g4x PCIe Gen3 x16 + 4x PCIe Gen3 x4 expansion slots80 PCIe 3.0 native links on backplane, without any additional switchCommunication between the SHB board and I/O boards with optimal latency times2x 800W redundant power suppliesMonitoring via the standard HMI of the OPALE V2 range7-years long lifeModified COTS services for OEMHDEC: but what does it mean exactly ?You already know what HPEC means: High Performance Embedded Computing, dear to high-end VPX fans. (See TOPAZE D) Now, you have to remember HDEC, High Density Embedded Computing by Trenton, the main contributor to PICMG 1.3 standard which has introduced the PCI Express protocol on a passive backplane in place of the ISA and PCI buses of the famous PICMG 1.0.In 2005, we thought that the 20 PCI Express link limit of the PICMG 1.3 standard, linking the SHB board directly to the backplane would be sufficient for very long years. But it shows very quickly its limits for dual processor server applications which require high bandwith and the shortest latency as possible. The extension solution consists in the integration of switch PCIe components on the backplanes to artificially increase the number of links, making the so-called backplanes less and less passive.In June 2014, the consolidation of the Embedded Market led to the takeover of the leader PLX by the American Avago. With a near-monopoly, the switches prices jumped leading to a dramatic increase of PICMG 1.3 backplanes for high end applications, going so far as to make them prohibitive.Trenton has to face the situation to find a native efficient and cheaper solution in order to relieve the pressure on the backplane.Especially since the current E5-2600 v3/v4 XEON Series (Haswell-EP/Broadwell-EP) currently provide 40 Gen 3 PCIe links, it means an 80 PCI Express 3.0 links “highway” potential output from a SHB Dual-Xeon arriving on a “departmental road” equipped with 20 links only on the backplane. The next 14nm Xeon (Skylake –EP) will offer native 44 links, that means 88 out of the next Tenton’s Dual-Xeon board.The issue came from the dual-density PCI Express plug-in connectors used by the HDEC ecosystem. The new HEP8225 SHB board (integrating two 14-Core Xeon with each 4 DDR4-2400 channels; 128GB max capacity) and the various backplanes are equipped with this new technology offering 80 and soon 88 PCI Express 3.0 links, 6x SATA/600, 6x USB and various power supplies, I/O for diagnosis… On the rear bracket, the board offers 2x 10G Ethernet, 2x 1G Ethernet, 4x USB 3.0, VGA, serial and audio ports.Benefits of this new technology offered by Trenton to the PICMG committee:88 PCI Express links, that means +340% increase versus the current PICMG 1.3;The aggregate bandwidth of the complete system multiplied by 5!Less reliance on PCI Express switches and Avago’s hegemony;Significant reduction in latency between the SHB and its bus I/O boards;Ideal for multi-FPGA, multi-GPGPU with PCIe X16 links applications;More power supply lines to deliver high end server processors;Opens the way to support increasingly powerful CPUs.The HDEC technology mostly meets the needs of goverment and defense applications, data concentrators, video applications, video walls, scientific computing.Find the Buildings Blocks of the OPALE V2-HDEC in our online catalogDownload our OPALE V2-HDEC datasheets: HEP8225 HDB8228
