By John Rhea
SAN DIEGO - Leaders of Space Electronics Inc. (SEI) in San Diego, are characterizing commercial off-the-shelf (COTS) 4-megabit memory chips to determine how far below 5 volts they can operate in spacecraft memory systems.
In a cooperative effort with NASA Jet Propulsion Laboratory (JPL) in Pasadena, Calif., SEI experts will submit standard CMOS static random access memories (SRAMs) to a series of electrical tests, initially at 5 volts, then to 3.3 volts, and then progressively lower to determine the effects of the lower voltages on speed and noise levels, says SEI President Dave Strobel.
The driving force behind the study is JPL`s New Millennium project to insert leading-edge technologies into future spacecraft. Strobel estimates the project will take about 36 man-months of effort, and is committing his company to deliver the findings in September. SEI will characterize about 20 parts from each of four vendors - initially from Motorola and Hitachi - and SEI experts are seeking two other companies.
It is a matter of tradeoffs, Strobel explains. Power is at a premium on a spacecraft, and a designer may accept an SRAM operating at 40 nanoseconds rather than 30 nanoseconds if the voltage can be reduced from 5 to 3.3 volts. It is also a matter of cost. Commercial 4-megabit SRAMs are running $40 to $50, but the space-qualified equivalent (including radiation hardening) runs around $300.
At the same time, SEI officials introduced what they claim is the first 3.3-volt 1-megabit CMOS electrically erasable programmable read only memory (EEPROM). The company had previously shipped 5-volt 1-megabit EEPROMs for spacecraft applications in which reconfigurability is important.
