UPPER SADDLE RIVER, N.J., 29 Aug. 2005. Pentek Inc. in Upper Saddle River, N.J., is offering an addition to its GateFlow field programmable gate array (FPGA) intellectual property (IP) library that implements a 256-channel narrowband digital downconverter (DDC).
Designed for use in Xilinx's Virtex II, Virtex II Pro or Virtex 4 FPGAs, the Model 4954-430 core offers 64 times the channel capacity of conventional quad ASIC downconverters, company officials say.
This IP core is for developers of applications requiring many digital downconverter channels with size, weight, cost, and power constraints, such as military radios and commercial wireless.
"This represents a huge boost in channel density," says Pentek Vice President Rodger Hosking. "In the past we have been limited to just a handful of DDC channels in a single device. The Model 4954-430 core delivers an extremely high channel-to-FPGA ratio, with density at least an order of magnitude higher than any other implementation available in either FPGA or ASIC form."
Accepting real or complex data samples at rates as fast as 185 MHz, the architecture uses a channelizer stage that generates 1024 fixed adjacent frequency channels with alias-free performance greater than 75 dB across the passband of each channel. A 256-output switch matrix follows the channelizer, providing a coarse tuning capability for the desired output channels.
Each of the 256 DDCs has a programmable numerically controlled oscillator (NCO) to implement independent fine-tuning for each channel and mixer to translate the signal of interest to baseband.
A decimating FIR low-pass filter then defines the channel bandwidth of the baseband output. The NCOs have a frequency resolution of 32-bits, and the baseband outputs pass through a programmable gain stage before being rounded to their final 16-bit result. Each channel has an independently programmable 16-bit gain control.
For more information contact Pentek online at www.pentek.com.
