VMETRO introduces low-jitter, 2 GHz multi-channel clock generator

June 16, 2007
HOUSTON, 16 June 2007. VMETRO in Houston is announcing a high-frequency clock generator PMC/XMC module, the XCLK1, that provides as many as five phase-matched, low-jitter sample clocks for high-speed analog to digital converters.

HOUSTON, 16 June 2007. VMETRO in Houston is announcing a high-frequency clock generator PMC/XMC module, the XCLK1, that provides as many as five phase-matched, low-jitter sample clocks for high-speed analog to digital converters.

The XCLK1, which runs at rates as fast as to 2 GHz per channel, generates fast clock sources in a small format suitable for high-performance embedded applications such as signals intelligence, spectral analysis, and radar.

High-frequency analog to digital converters require stable, low jitter clock sources, which until now have tended to be bulky. By shrinking this functionality into a space that can be accommodated by any industry standard PMC or XMC site, multi-channel signal acquisition can now be more cost effective and requires less space.

The XCLK1 offers internal or external clock reference sources. The default clock source is an onboard 10 MHz TCXO (temperature compensated crystal oscillator). Local frequency multiplication based on this reference can generate output signals in the range of 500 MHz to 2 GHz with a jitter of less than 0.5 picoseconds. The output clock is available through five single-ended or three differential front panel outputs. Alternatively, the XCLK1 can derive its outputs from an external source; either a front panel RF (0 to 2 GHz) input, 10 MHz front panel reference or 10 MHz from its PMC user I/O connector.

When providing a clock source to multiple acquisition cards, users often need to synchronize the trigger, or start of acquisition for all cards, so that multiple samples are coherent. This is important for applications such as beamforming. The XCLK1 helps solve this problem by being able to momentarily halt all sample clock outputs using its trigger/reset input. This gives time for all acquisition cards to be reset and to start to capture data synchronously. Releasing all the clock outputs at once ensures that all data flows start together and are in step.

For more information contact VMETRO online at www.vmetro.com.

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