The new frontier of system-on-chip redefines the boundaries of integrated circuit test, as developers struggle to keep IC development and built-in test on parallel tracks
By John H. Mayer
Integrated circuit manufacturers are migrating to a new generation of quarter-micron process technologies, and vendors are filling their libraries with a growing array of cores. Evidently the long-anticipated system-on-chip (SOC) revolution has arrived. Yet the move to tightly integrated SOC designs is placing an increasing burden on the integrated circuit test community. Microelectronics test experts today face demands for automatic test technology capable of handling ever-more-complex integrated chip systems that include high-speed logic, embedded memory, as well as analog and mixed-signal.
Maturing merged memory and logic processes are finally enabling integrated circuit designers to take extensive advantage of embedded dynamic random access memory (DRAM), while original equipment manufacturers in a variety of market segments are mounting more analog and mixed-signal functions on-chip.
Analysts from market research firms such as Dataquest in San Jose, Calif., estimate that very deep submicron (VDSM - defined as 0.35-micron or smaller) designs account for more than half of all integrated circuit design starts and are expected to grow to 90 percent by the year 2000. In fact leaders of some leading integrated circuit manufacturers such as IBM Microelectronics Inc. of Essex Junction, Vt., are already seeing average chip densities running in excess of the 1 million gates.
At the front edge of the technology curve are many military and aerospace designers. "We`ve seen a huge expansion in digital processing in space driven largely by the tremendous growth in integrated circuit densities from about 15,000 gates in the early `80s up to the 4 million-plus gates that are available today," notes Brian Clebowicz, digital electronics operation manager at Hughes Space and Communications in Los Angeles.
Lasting influence
The evolution to tightly integrated SOC design has opened new opportunities for integrated circuit designers to improve performance and add functionality. It also has also raised the bar to a daunting new level for automatic test equipment (ATE) manufacturers. To meet customer needs, they are now being asked to deliver integrated systems that not only can handle high-speed logic, but embedded memory and mixed-signal functions as well.
"When the core functions were separate, a tester could get away with not having, say, memory test," observes Dan Simpkins, market analyst for the VLSI test division at Teradyne Inc. in Boston. "But with today`s VLSI device having potentially some memory, some analog, and certainly a lot of logic on it, that ATE system now truly has to have a very wide ranging capability."
Most ATE vendors are well down that road. Teradyne`s J973 tester, for instance, supports as many as 1,024 pins and features a pattern integrator architecture that provides a high-speed pattern bus that interleaves logic, memory, and scan patterns on any pin, at speed.
The Teradyne J973 tester also synchronizes analog sources with logic patterns. Teradyne`s Catalyst tester, a second system offering mixed-signal and embedded memory capability, is seeing use at aerospace system manufacturers such as Rockwell International Corp. in Newport Beach, Calif., and research organizations like Sandia National Laboratories in Albuquerque, N.M., to test and characterize communications and integrated micro-electro mechanical system devices respectively.
Other ATE vendors are offering comparable offerings. Officials of Advantest Corp. in Buffalo Grove, Ill., recently brought to market the T6682 VLSI test system for integrated circuits with mixed-signal capability, embedded memory, or high-speed interface technologies such as Rambus or IEEE-1394 Firewire. The tester supports data rates as fast as 1 GHz and at-speed testing of more than 1,024 channels.
Leaders of Hewlett Packard of Palo Alto, Calif., offer a wide range of integrated circuit test systems at different prices for SOC and mixed-signal test. Their latest entry, the Model 95000 memory tester, offers 1 GHz data rates designed to meet the demanding test requirements for emerging Direct RDRAM memory integrated circuits.
Chip and system manufacturers such as Sun Microsystems in Mountain View, Calif., are turning to testers like the ITS9000IX from Schlumberger ATE in San Jose, Calif., to test high-performance integrated circuits and microprocessors. Meanwhile, experts at National Semiconductor Corp. of Santa Clara, Calif., are using the Fusion HF tester from LTX Corp. in Westwood, Mass., to characterize SOC devices. Meanwhile, military prime contractor Raytheon uses testers from Credence Systems Corp. in Fremont, Calif., for mixed-signal and RF test.
While ATE vendors believe they are well positioned to meet the I/O needs of today`s high-pin-count SOC devices, keeping pace with their rapidly escalating speed requirements is another story. "Until the last couple of years, most bus speeds going off chip were within the 100 to 200 MHz range," notes Teradyne`s Simpkins. "Now people are proposing very high performance bus speeds for even the PC main memory with concepts like Rambus."
Speed is a particular challenge. "As clock frequencies go higher, at-speed test to assure that the performance of a chip meets the customer`s specification probably presents the greatest challenge we face," says Dr. Hitosh Yoshizawa, chief manager of the system integrated circuit business at NEC Electronics Inc. of Mountain View, Calif.
Rapidly increasing clock speeds "caught us all off guard about year and a half to two years ago," admits Rick Carmichael, senior vice president of corporate marketing for Credence. "Things jumped up at a level that no one anticipated. It seemed like we went by the mid-hundreds in the blink of an eye."
Teradyne`s J973 already supports data rates beyond 800 MHz. "But we`re going to have to accelerate our plans to keep up with what could happen should Rambus be rapidly accepted into the market," Simpkins admits.
Experts at Credence are taking an instrument approach to support high clock rates. "If you build a tester around the outside envelope of everything a system can do today, you`d end up with a $4 million or $5 million tester and no one would buy it," Carmichael notes. "So you have to look at creative ways to segment functionality rather than have all the pins on the tester do it."
New game
However ATE vendors plan to attack the problem, there is a general consensus that the emergence of SOC technology will mark a fundamental turning point for ATE architectures and test methodologies. One key question will be whether widely accepted scan and automatic test-pattern generation (ATPG) techniques will be able to cope with the rising chip complexity as integrated circuit manufacturers migrate to very deep submicron processes.
Many industry observers, in fact, expect to see a growing shift to structural test in next generation ATE architectures- as vector rates for full functional test stress the ability of current tester architectures and as pressures escalate to reduce the per-channel cost of testers.
Key to that development, say some, is an increasing use of built-in self-test (BIST) technology. BIST proponents argue that test methodologies built around the use of scan and ATPG face the prospect of increasingly large and expensive data sets as chip density explodes. Moreover, they are reliant on accessibility assumptions that are no longer a given in a design environment where a function that used to reside on a discrete chip may now be buried inside an IP block developed by some third party vendor.
Creeping device complexity, however, is frustrating some test engineers. "Even if you succeed in building an integrated tester for SOC devices, the silicon is kind of drifting away from you," argues Berne Koenemann, vice president of products and solutions with LogicVision, Inc. in San Jose, Calif., a supplier of embedded ATE solutions. "The processor core that previously was a discrete processor now sits in the middle of some system chip and you cannot even talk to it unless there is support circuitry implemented on the chip that connects the tester back to the core."
To help cut test development and manufacturing test costs of VDSM devices, LogicVision engineers have developed an embedded ATE solution for at-speed test and diagnostics of digital and mixed-signal SOC devices. As part of the LogicVision integrated suite of embedded ATE capabilities, icBIST 3.0 supports at-speed test of high-speed logic, mixed- signal and legacy cores, and test and diagnostics of board-level interconnects and memory arrays.
LogicVision`s technology proved instrumental in the rapid development of the Hughes Geomobile (GEM) family of communications satellites that features a 12.25-meter deployable reflector, on-board digital signal processing, circuit switching, and digital beamforming. Designed to serve portable cellphone-sized telephones, GEM contains an on-orbit reconfigurable digital processor.
Since the late 1980s, Hughes satellite designers have progressed through a series of test methodologies to meet the challenges presented by increasingly dense SOC devices, Clebowicz says. With integrated circuits in the 15,000-gate range in the late 1980s and early 1990s, Hughes engineers used a simple functional test approach. "We basically ran test vectors through the parts that represented what they were going to be doing in the application and got maybe 80 percent fault coverage if we were lucky," Clebowicz remembers.
Hughes shifted to simple scan-based methodology about 1992 and got fault coverage of as much as 90 percent. Designers began to use vertically integrated testability based on IEEE 1149.1 boundary scan in 1993 when Hughes developed one of the first very large-scale digital processing commercial payloads, a system that was comprised of more than 2,300 integrated circuits of about 150,000 gates each.
On the current generation of the GeoMobile payload, Hughes also built in 1149.1. But since the design called for integrated circuits as large as 4 million gates, it was no longer possible to load the test vectors through the 1149.1 ports and run the tests using a reasonable number of vectors, Clebowicz explains.
"We found that once our design starts to get over about one-half million gates, the time and memory involved becomes prohibitive," Clebowicz explains. "So we adopted a strategy of BIST where we can initiate self test through the 1149.1 port and then collect a signature. This has greatly reduced the amount of testing we have to do and the number of vectors we have to transfer over this interface." Fabricating the chip was IBM Microelectronics of Essex Junction, Vt., in the company`s SA-12 0.25-micron process shortly after the integrated circuit manufacturer integrated LogicVision`s icBIST into its integrated circuit design flow.
Through this progression of test methodologies Hughes officials have seen the complexity of their test equipment shrink dramatically while the speed of test has greatly accelerated. "And along the way we`ve gone from functional testing where we had 80 percent fault coverage at best to the use of BIST where we`re getting better than 99 percent fault coverage," notes Clebowicz.
The use of BIST has not been limited to the Hughes commercial satellite programs. Company engineers are incorporating the technology into integrated circuits on the Advanced DHF Engineering Model project, a follow-on to the MILSTAR program that will develop highly protected, anti-jam, low probability of intercept and detection communications systems for tactical and strategic military users. Hughes and TRW have the two engineering model contracts for development of a system processor.
Despite success stories like the GeoMobile, the growing use of BIST does not sound a death knell for traditional ATPG approaches test vendors say. Most believe it will continue to offer the best methodology for testing complex integrated circuit designs. And those who do not still expect it to be used selectively.
For instance, even LogicVision`s icBIST includes ATPG for I/O and test of the self-test circuits. And many believe ATPG will continue to play an important role at the core level in SOC designs even if it proves not to be cost-effective at the chip-wide level. "There`s going to be a mix and match as people try to optimize cost around their test and design flows and what they have in their factory," Koenemann says.
"BIST is still a newer technology and pretty much limited to higher integration projects," says Teradyne`s Simpkins. "From what our customers say, you have characterized BIST to know how to guardband for its test results much like you have to guardband for a tester`s measurement accuracy."
Although BIST offers several advantages, it also carries its own set of liabilities. One of the most disputed is its cost. Chip designers pay a price in silicon overhead when they implement BIST on-chip, and ATE vendors repeatedly note that it is rarely cost-effective to ship test circuitry with each device.
While some argue that the move to deep submicron processes raises the cost of BIST, the technology`s proponents argue otherwise. "What we find is a good solid ATE solution that gives you sufficient flexibility, diagnosability, and test coverage in a manufacturing test environment takes something on the order of 10,000 gates on a chip," claims Logic-Vision`s Koenemann. "On the other hand if you talk to people who know how much test equipment costs, they`re usually willing to give you somewhere between half a percent and one percent of their silicon in their design as a tradeoff for embedding the ATE function not including infrastructure like scan which can be used with external equipment just as well as embedded equipment."
One point Koenemann emphasizes is that as integrated circuit manufacturers pack more transistors on chip, the percentage of the design dedicated to BIST will decrease. "That`s because the functions that we build in do not necessarily scale linearly in proportion to the gate count," he explains. "So whereas traditional test equipment is challenged by the continual renewal and improvement in semiconductor technology, our technology gets easier to implement the more technology you throw at us."
BIST`s performance capability is also an arguable point. Neil Kelly, chief technologist at LTX Corp., notes that continual efforts to reduce the silicon area that BIST uses can reduce its functionality by forcing the designer to compromise between test-effectiveness and silicon area. He also observes that BIST usually generates signals at nominal voltages and timing, and since the circuitry cannot vary the signal, it cannot perform the more complex analysis an external tester can provide. That could result in the inability of the test circuit to detect race conditions among virtual components in a SOC device and force the designer to over design to compensate for the effect of process tolerances.
In addition, while BIST has seen wide utility for the memory test, it faces significantly more skepticism on the logic side. Many believe that as device speeds rise and the signal levels between virtual components in an SOC become more and more critical, it may not be able to meet a designer`s needs. But Koenemann attributes that to lack of exposure. "There`s skepticism mainly because it mainly hasn`t been economically attractive in the past to use BIST to test logic, so many designers haven`t been exposed to it," he argues.
Another consideration has been an absence of automated tools and design methodologies to implement BIST. LogicVision has begun to address that with its icBIST product. Meanwhile, Mentor Graphics Corp. of Wilsonville, Ore., recently bought to market new technology that enables designers to insert BIST into complex memories in a single step.
On a more comprehensive scale, LogicVision officials recently announced SOCKET, a comprehensive way for testing core-based SOC devices. The solution, a service option to the LogicVision icBIST technology, provides a reusable test methodology to improve designer productivity. It enables engineers to create hierarchical, plug-and-play test and diagnostic capabilities. At the core design phase, SOCKET enables the developer to prepare each core with a reusable test capability and a test information model. Later, as the chip is designed, SOCKET creates a total test approach by integrating the re-usable core test with additional test capabilities for top-level, user-defined chip functions.
System-level test
While the debate rages on about the merits of BIST, particularly for logic in the SOC arena, there is widespread recognition that its extensibility and reusability can provide powerful advantages at the subsystem and system level. This has proved particularly true in applications where remote diagnostics and repair are critical system requirements. "The key thing that people miss about BIST and testability in general," notes Clebowicz, "is that it is very advantageous to be able to link all the digital circuitry as one block in a vertically integrated test."
On Hughes GeoMobile program, for example, hierarchical BIST structures on the payload`s integrated circuits are coupled together at the board level. Hughes then developed its own TAP controller as well as a scan bridge to enable testing of integrated circuit integrity and the interconnects between the integrated circuits via a serial interface on each board. The architecture then extends vertically to the entire unit that is accessible through a single serial connector. "It`s allowed us for the first time to plug into a unit that was fully assembled and probe any part," Clebowicz says.
One of the key benefits, he notes, comes in a shorter production cycle. In a recent project where Hughes had to produce 12 very complex satellites for a customer in a very short time, BIST enabled the test engineers to probe the units and subsystems rapidly. "It simply took seconds whereas some of the older functional methodologies would have taken hours," Clebowicz says.
The next step for Hughes will be making all the data and control available in orbit through a telemetry and control interface to the integrated circuits called Cbus. That will enable satellite operators to troubleshoot the system and run preventive diagnostics to predict which parts are aging the quickest. "Many of our customers are astounded that we can provide this capability," admits Clebowicz.
The other obvious advantage of such vertical integration is simple reusability. "If you add all those testability features to your integrated circuits and you`ve got them there on the board, it seems a shame to just use them once," says Brain Stearns, product marketing manager for National Semiconductor Corp. of South Portland, Maine.
National played a pivotal role in the development of a vertically integrated built-in structured test architecture used in the Motorola Iridium communications satellites. Hughes designers faced the daunting challenge of building 66 low-Earth satellites for a global communications network on a production schedule that called for the completion of one satellite per week. So the Motorola team decided to adopt a structured test approach that would support extensive test reuse by emphasizing consistency across all designs and would be hierarchical across all levels of integration. Thus, in addition to adopting a design for test strategy for individual integrated circuits based on 1149.1 boundary scan, designers extended the same architecture to the system level by using a dedicated backplane that ran parallel to the system backplane.
Two commercial off-the-shelf devices from National Semiconductor were key to that implementation. The PCS110 scan bridge acted as an addressable scan port on each board and managed the scan path. The PCS100 boundary scan controller- converted 8-bit test vectors to serial and back again. "So while they had gone to the trouble to buy these tools and incorporate these tests on chip, they can now, for a fairly minor additional investment, use them throughout the program," Stearns says.
Repartitioning functions
Where will these evolving test challenges drive ATE in the near future? As providing high fault coverage for large and complex devices becomes increasingly difficult, many see a transition from a more functional to a more structural approach to test. But ATE vendors see a much more gradual transition than BIST adherents do.
"People are talking about structural test taking over and saying that tests will become much simpler because you`ll be able to rely on techniques like scan and BIST to deal with fault coverage and speed grading," Simpkins says. "I think BIST, scan and iddq [the measurement of quiescent current in CMOS used to incrementally increase fault coverage or identify potential failure mechanisms] will all be used more and more over time, but I don`t see a cliff where one day we`re going to go from functional test to BIST. I see a very slow transition."
"What we`ll see is a repartitioning of the test function between the silicon and the tester," argues Koenemann. But he agrees the transition will be gradual and depend highly on what an integrated circuit manufacturer already has on the test floor. "People will make tradeoffs. For example, if I have a good logic tester and I can address the problem that way, but I don`t have a memory tester, it may make a lot more sense for me to integrate memory self test, but not necessarily logic self test."
Ultimately, however, he sees an end to larger and ever more expensive ATE. "My prediction is the testers in the year 2003 will be a lot smaller than they are today, a lot better integrated with support equipment such as handlers and probers, and will actually be partitioned into integrated embedded ATE on the chip, support functions on the interface structure such as the probes or performance board, and the tester itself."
ATE vendors do not necessarily disagree with that view. "I think the fundamental process is one of containing the problem into sizable chunks," says Credence`s Carmichael. "It`s really the only way to keep the testing in hand. That doesn`t mean you`re going to eliminate the tester - people have been predicting that since the 1970s. But it says we`re going to have to use things like BIST to keep the demands of the tester within range because without it a $40 million ATE system could be a reality."
The challenge for ATE vendors will be how to redesign their tester architectures to support a shift from functional to structural test without increasing cost. Simpkins says he believes that might drive ATE vendors from having similar high-end capability on every tester channel to a limited set of tester channels with high-end capability and a broad set of tester channels with very simple capability. "That way you could pack more simple tester channels into a test system and move to very, very high pin counts," he notes. "But the challenge will be how to define what the requirements are of those low capability channels."
In the meantime, if self test will play a larger role in the test process, vendors have a lot of work to do on simplifying the transfer of information from the SOC designer to the test floor.
While standards groups like the Virtual Socket Interface Association and IEEE P1500 are working on the interface between the core developer and the system chip integrator, there is still a missing link between the system chip integrator and the test engineer on the manufacturing floor. "We believe the side of test that`s most lacking is how do you move from the engineering design environment into the production test environment with more certainty," Carmichael says. "Right now it`s a very labor intensive and error-prone process."
To address that issue Credence recently signed an agreement with LogicVision. The agreement calls for the companies to develop products together that will link Logic-Vision`s embedded ATE solutions with Credence`s integrated circuit testers. The production test software will create and execute optimized embedded ATE tests.
Today that information transfer is largely missing Koenemann says. "You talk to integrated circuit vendors and they run into problems and oftentimes have no clue which part of the circuit was tested," he says. "So they have to go back to the design engineer or the tool vendor."
LogicVision`s icBIST 3.0 embedded ATE solution provides at-speed test and diagnostics for random logic, embedded memories, mixed-signal cores at the chip level, and for chip I/Os, interconnects, and memory at the board level.
Analysts from the Dataquest market research firm say they expect very deep submicron SOC designs to become commonplace in the ASIC industry over the next several years.
The automatic test equipment market is expected to continue its rapid growth, as ASIC manufacturers struggle to achieve high-quality testing with conventional test methodology.
Representative of a new class of testers for SOC devices is the Advantest T6682, which supports data rates as fast as 1 GHz and at-speed testing of more than 1.024 channels.
One of the test challenges that very deep submicron ASIC designs present is the growing use of embedded memory in complex SOC designs.
