Georgia Tech continues work in high-performance computing to simulate complex RF and microwave test range
SAN DIEGO – U.S. Navy researchers needed a new kind of high-performance computing (HPC) system to help simulate a high-fidelity RF environment for a large-scale virtual RF test range. They found their solution from Georgia Tech Research Corp. in Atlanta.
Officials of the Naval Information Warfare Center Pacific in San Diego announced an $11.5 million order to Georgia Tech on Wednesday to move forward with a project to develop a new breed of high performance computer (HPC) called Real-Time HPC.
This new high-performance computer architecture seeks to balance computational throughput with extreme low latency to create a large-scale virtual RF and microwave test range. This order increases the Real-Time HPC contract value to $13.9 million.
This project builds on work by the U.S. Defense Advanced Research Projects Agency (DARPA) in Arlington, Va., called Digital RF Battlespace Emulator (DRBE), which seeks to deliver the scale, fidelity and complexity necessary to match how complex sensor systems are employed today, and provide a valuable military development and testing environment.
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Testing, evaluation, and training of future military systems increasingly will happen in virtual environments because of rising costs, system complexity, and the limited availability of military ranges, DARPA researchers explain.
Virtual simulators already are used to augment real-world training for modern fighter aircraft pilots, and they hold significant promise for addressing the demands of testing and training artificial intelligence (AI)-enabled technologies.
Today's simulated test range environments, however, rely on conventional computing that are unable to generate the computational throughput and speed to replicate real-world interactions, model the scale of physical test ranges, or meet the technical requirements of more complex systems, experts say.
To address those computing limitations, Georgia Tech researchers helped DARPA create the DRBE, which Georgia Tech now is extending and refining under supervision of the Naval Information Warfare Center Pacific.
Georgia Tech researchers will design computing architectures and domain-specific hardware accelerators for future simulations of complex RF environments.
Existing high-performance computers rely on general-purpose computing devices like general-purpose graphics processing units (GPGPUs) or field-programmable gate arrays (FPGAs), which put a priority on high computational throughput at the expense of latency, or have very low latency and low computational throughput.
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Georgia Tech researchers will try to overcome those limitations by creating a new breed of high-performance computing hardware that combines the best traits of GPGPUs and FPGAs.
Georgia Tech also will develop tools, specifications, and interfaces to integrate a real-time high-performance computing system, and create a virtual RF test range.
On this order George Tech will do the work in Atlanta, New York, and Aurora, Colo., and should be finished by July 2024. For more information contact Georgia Tech Research Corp. online at https://gtrc.gatech.edu, the Naval Information Warfare Center Pacific at www.niwcpacific.navy.mil, or DARPA at www.darpa.mil.
John Keller | Editor-in-Chief
John Keller is the Editor-in-Chief, Military & Aerospace Electronics Magazine--provides extensive coverage and analysis of enabling electronics and optoelectronic technologies in military, space and commercial aviation applications. John has been a member of the Military & Aerospace Electronics staff since 1989 and chief editor since 1995.
