- Computers
Intilop debuts TCP Offload Engine offering low latency using Altera Stratix IV FPGA
SANTA CLARA, Calif., 20 Feb. 2012. Intilop Inc., maker of complex ultra-low-latency networking Mega IP building blocks and systems, is introducing its 4th Gen. SX-Series 10G ultra-low-latency TCP Offload Engine (TOE) + EMAC + Altera PHY Mega IP cores running on a Stratix IV field-programmable gate array (FPGA). The TOE’s architecture is scalable, customizable, and adaptable. Intilop’s product-line solutions are available in flexible FPGA/ASIC/SoC technologies, which can accommodate a diverse set of technical design specifications.