Integrated circuits, digital - IP cores

The SPI Master Core implements a master and the SPI Slave Core implements a slave as specified in Motorola's M68H11 Reference Manual to DAL-A according to the DO-254.

The SDRAM Controller Core implements an SDRAM Controller to interface to an SDRAM device compliant to the JEDEC Standard No.21-C Page 3.11.5.1 Release 9 to DAL-A according to ...

The A429 Rx Core implements a receiver and the A429 Tx Core implements a transmitter as specified in the ARINC Specification 429 Part 1-17 to DAL-A according to the DO-254.

The CAN Core implements a CAN as specified in the CAN Specification 2.0B (Bosch, Sep 1991). The optional Time Triggered Communication (TTC) as specified in the ISO-11898-1 is ...

The MIL-STD-1553B RT Core implements a Remote Terminal as specified in the MIL-STD-1553B (DoD, 21 Sep 1978) with Change Notices (1 through 7). Basic Bus Monitoring capabilities...